When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, high k dielectric material and metal are adopted to form a gate stack. However, in a method to form metal gate stacks for n-type MOS (nMOS) transistors and p-type MOS (pMOS) transistors, various issues may arise when integrating the processes and materials for this purpose. For example, when a p-type metal gate of a pMOS transistor is exposed to a polysilicon removal process at a step to form an n-type metal gate, aluminum filled in the p-type metal gate is damaged and recessed. As such, an n-type metal layer may be non-uniformly deposited in the recessed p-metal gate. This causes high resistance of the p-type metal gate. Furthermore, the non-uniformity of the p-type metal gate causes device performance variation. Therefore, there is a need for a fabrication method to address the above concerns.